The PCIe v3.0 architecture offers notable improvements over PCIe v2.0 and optimizes the trade-offs between manufacturability, cost, power, complexity, and compatibility. The update doubles the interconnect bandwidth, offering a 128-bit/130-encoding scheme and a data rate of 8 gigatransfers per second (GTps). With the data rate expansion, “It is possible for products designed to the PCIe 3.0 architecture to achieve bandwidth near 1 gigabyte per second (GB/s) in one direction on a single-lane (x1) configuration and scale to an aggregate approaching 32 GB/s on a sixteen-lane (x16) configuration,” according to Benchmark Reviews. PCIe v3.0 is fully backward compatible with previous PCIe architectures and is optimally designed for high-volume platform I/O implementations.
“Each new version of the PCIe spec has doubled the bandwidth of the prior generation,” said Nathan Brookwood, research fellow at Insight 64, in a press release. “The latest group of PCIe architects and designers drove the standard forward while maintaining complete backward compatibility for Gen 1 and Gen 2 devices. Rarely has a standard advanced so non-disruptively through three major evolutionary cycles. The ability to pull this off demonstrates not only the ingenuity of the Gen 3 developers, but also the insight of those who defined the earlier versions in such an extensible manner.”
We’re excited that the wait is over, and we look forward to helping developers deliver exciting new PCIe products with our PCI testing services.
